Variable frequency control has been widely used in DC-DC power converters since variable frequency control provides not only improved light load efficiency but also fast transient response and high bandwidth design to reduce capacitance requirements for filter capacitors; saving cost and size. The light load efficiency is increased by reducing switching frequency, fsw, when the load current decreases and thus reduces switching losses. The transient response is improved by allowing fsw to change quickly during a rapid load current change. The higher control bandwidth on the output voltage feedback loop is obtained due to eliminating the aliasing effect of constant frequency control. The three most common types of variable frequency control are constant on-time (COT), ramp pulse modulation (RPM) control and hysteresis control.
However, wide variation of switching frequency in response to variation in input or output voltage change, as is presented, for example, by state-of-the-art laptop computer processor designs which use narrow VDC (NVDC) techniques to lower the input voltage range that can be supplied from serially connected battery cells, is inherent in variable frequency controlled power converters. For example, in view of possible scaling of output voltage operating points, Vo of a DC-DC converter from 0.5 V to 2.0 V, the duty cycle, D=Vo/Vin, for a buck converter, can range from 0.06 to 0.4. Using COT control, since on-time, Ton, is fixed, the frequency can vary over a range approaching a decade in frequency (e.g. from 800 kHz at D=0.06 to 5.3 MHZ at D=0.4).
However, such a wide frequency range causes excessive power losses and problems with achieving correct interleaving angle for multi-phase operation. To reduce such power losses, it is known to provide a frequency regulation loop to slowly adjust Ton to maintain operation in a manner somewhat similar to constant frequency operation. In other words, when duty cycle is increased or decreased, the frequency change is reduced by changing the on-time slowly such that the frequency is held to a more nearly constant value to compensate for the difference between the required frequency for COT operation and the frequency at which the converter actually operates, referred to as pulse frequency modulation (PFM). For a given duty cycle, the switching frequency varies inversely with Ton and thus the switching frequency can be adjusted by changing Ton.
For multi-phase operation where a plurality of power converters are essentially connected in parallel, it is common practice to interleave the pulses created by the switching within the respective power converters to equalize time intervals between pulse frequency modulation (PFM) pulses from respective converters. Arrangements for such interleaving with a frequency regulation loop generally fall into one of two types: pulse distribution structures and phase-locked loop (PLL) structures.
In a pulse distribution structure, the frequency regulation loop is implemented by Vin and Vo feed forward to the on-time generator. The interleaving is achieved easily by distributing the pulses which result from the intersection of the sum of inductor currents of all phases and the control voltage, Vc. However, transient response is slow because the phase manager (sometimes referred to as a phase splitter) arrangement, as will be discussed below, cannot immediately synchronize PFM pulses of all phases during step-up load transients. Further, pulse distribution structures exhibit noise sensitivity due to ripple cancellation between the sum of the instantaneous currents delivered by the respective phases, particularly since the power delivery pulses do not overlap. At operating points where ripple is substantially canceled, low-level noise can cause duty cycle jittering and results in higher output voltage ripple. Adding an external ramp voltage having a slope Se can reduce jittering but the strong phase delay caused by using the ramp signal reduces the phase margin of the output voltage feedback loop and limits bandwidth. For example, FIG. 1A shows the resultant loop gain of output voltage feedback loop (T2), which indicates that even a small Se reduces the phase margin to less than 60° when the bandwidth (e.g. the frequency that produces zero gain in the transfer function of the loop, also referred to as the crossover point) is designed close to fsw/6. Also, when the duty cycle changes, the phase delay effect becomes stronger. Thus, high bandwidth design becomes more difficult for a wide range of duty cycle, as shown in FIG. 1B. As a result, poor transient performance and poor stability margin requires large output capacitance for acceptable operation of pulse distribution structures. The same issues are present in COT control, RPM control and hysteresis control.
On the other hand, phase locked loop (PLL) structures have the advantages of exhibiting faster transient response, less noise sensitivity and higher bandwidth of the output voltage feedback loop. In PLL structures, a PLL is provided as a frequency regulation loop in each phase and is arranged to adjust Ton to track a fixed frequency clock signal. Interleaving is achieved by shifting the phase of the fixed frequency clock applied (and to which respective PLLs of each phase are synchronized/locked) by an angle determined by the number of phases employed. The modulation is determined by the intersection of individual (rather than total, as in pulse distribution structures) phase current and control voltage, Vc, such that the Vc increment during a large step-up load transient causes early intersection with the current feedback signals of each phase to be closely spaced in time; forcing the PFM pulses to immediately begin to overlap during large load transients. Further, PLL structures do not exhibit a ripple cancellation effect, do not require an external ramp signal for reliable operation and are less sensitive to noise than pulse distribution structures. Without the requirement for an external ramp signal, it is possible to maintain sufficient phase margin for stability in a high bandwidth design of the output voltage feedback loop as shown in FIG. 1C. PLL structures are known for use with COT control and hysteresis control. However, no applications of PLL structures are known or found in the literature for RPM control.
However, two drawbacks limit the adoption of PLL structures. Compensation of the PLL loop to be stable is difficult as will be discussed in greater detail below. Also, each phase requires a PLL and a high speed current loop comparator which lead to much increased complexity and cost as the number of phases is increased. Additionally, a PLL that alters on-time in order to track the frequency of a fixed frequency clock is, itself, of substantial complexity as will be discussed in greater detail below.